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• 19:41, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5292 of page Paper/Thesis Checklist patrolled
• 19:36, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5291 of page Paper/Thesis Checklist patrolled
• 19:31, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5290 of page Paper/Thesis Checklist patrolled
• 19:24, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5289 of page Paper/Thesis Checklist patrolled
• 19:23, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5288 of page Paper/Thesis Guide patrolled
• 00:25, 28 May 2015 Mrg (Talk | contribs) deleted page DFM Tutorials (content was: "==Mentor LFD == How to use LFD" (and the only contributor was "Mrg"))
• 00:24, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5287 of page Tutorials patrolled
• 00:24, 28 May 2015 Mrg (Talk | contribs) deleted page CMPE122/222 (content was: "These tutorials were adapted with permission from James Stine at OSU. The originals are available at [http://vlsiarch.ecen.okstate.edu/VLSI/]. === Magic === === N..." (and the only contributor was "Mrg"))
• 00:23, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5286 of page Standard-Cell Tutorials patrolled
• 00:23, 28 May 2015 Mrg (Talk | contribs) deleted page Other Technology Setups (content was: "Here are technology files to work with the General Synopsys Synthesis Script: == setup_osuami35.tcl == <pre> set OSUcells [format "%s%s" [getenv "OSUcells"] "/lib/a..." (and the only contributor was "Mrg"))
• 00:23, 28 May 2015 Mrg (Talk | contribs) deleted page OSU Technology Setup (content was: "For CMPE 222, we are using the [http://avatar.ecen.okstate.edu/projects/scells Oklahoma State University (OSU) design flow].<BR> You can build a reference design like this: *cp -rf /mada/software/techfiles/osu_soc_v2.7/synopsys/flow/am...")
• 00:22, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5285 of page Standard-Cell Tutorials patrolled
• 00:22, 28 May 2015 Mrg (Talk | contribs) deleted page Library Modification/Creation (content was: "== Accessing OSU Library contents using Cadence Virtuoso == # Go to /mada/software/techfiles or to the OSU VLSI computer architecture website http://vcag.ecen.okstate.edu/projects/scells/ to get the library tar file named osu_soc_v2....")
• 00:20, 28 May 2015 Mrg (Talk | contribs) automatically marked revision 5284 of page Standard-Cell Tutorials patrolled
• 00:20, 28 May 2015 Mrg (Talk | contribs) deleted page Primetime (content was: "Primetime is the sign-off timing analysis tool from Synopsys. It's interface is nearly identical to Design Compiler, but it is specifically for timing analysis. You will use the detailed parasitic file (.dspf), the Synopsys design constr...")
• 00:20, 28 May 2015 Mrg (Talk | contribs) deleted page Advanced Synopsys Design Compiler (content was: "== Back Annotation == Back-annotating extracted parasitics from placement into timing analysis using read_parasitics. == Simulating with Delays == Writing Standard Delay Format (SDF) for timing-aware Verilog simulation using write_sdf ...")
• 00:19, 28 May 2015 Mrg (Talk | contribs) deleted page Synopsys Design Compiler (content was: "== Introduction == This tutorial is intended to familiarize you with the logic synthesis tool called Design Compiler (DC) from Synopsys. It is not absolutely necessary that you understand Verilog, but it is helpful that you know some ve...")
• 00:17, 28 May 2015 Mrg (Talk | contribs) deleted page General Synopsys Synthesis Script (Copyright violation: content was: "<pre> sh date # set some per design variables set TOPLEVEL "lfsr" set LOG_PATH "log/" set GATE_PATH "gate/" set RTL_PATH "verilog/" set STAGE "final" set CLK "clk"..." (and the only contributor was "[[Special:C...)
• 22:08, 27 April 2015 Mrg (Talk | contribs) automatically marked revision 5283 of page Hardware patrolled
• 22:08, 27 April 2015 Mrg (Talk | contribs) automatically marked revision 5282 of page Hardware patrolled

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