Difference between revisions of "Standard-Cell Tutorials"

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# [[Simulating Verilog]]<BR>
 
# [[Simulating Verilog]]<BR>
 
# [[Cadence Encounter]]<BR>
 
# [[Cadence Encounter]]<BR>
 +
# [[Primetime]]<BR>
 
# [[Hierarchical Design and Floorplanning]]
 
# [[Hierarchical Design and Floorplanning]]
 
# [[Library Modification/Creation]]
 
# [[Library Modification/Creation]]
  
 
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].
 
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].

Revision as of 00:40, 17 February 2011

  1. OSU Technology Setup
  2. Other Technology Setups
  3. Synopsys Design Compiler (General Synopsys Synthesis Script)
  4. Advanced Synopsys Design Compiler
  5. Simulating Verilog
  6. Cadence Encounter
  7. Primetime
  8. Hierarchical Design and Floorplanning
  9. Library Modification/Creation

For other tutorials, please see the OSU wiki.