Difference between revisions of "Standard-Cell Tutorials"

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# [[Synopsys Design Compiler]]<BR>
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# [[Simulating Verilog]]<BR>
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# [[Cadence Encounter]]<BR>
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# [[Hierarchical Design and Floorplanning]]
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For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].

Latest revision as of 00:23, 28 May 2015

  1. Simulating Verilog
  2. Cadence Encounter
  3. Hierarchical Design and Floorplanning

For other tutorials, please see the OSU wiki.