Difference between revisions of "Standard-Cell Tutorials"

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# [[OSU Technology Setup]]<BR>
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# [[Synopsys Design Compiler]]<BR>
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# [[Advanced Synopsys Design Compiler]]<BR>
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# [[Simulating Verilog]]<BR>
 
# [[Simulating Verilog]]<BR>
 
# [[Cadence Encounter]]<BR>
 
# [[Cadence Encounter]]<BR>

Latest revision as of 00:23, 28 May 2015

  1. Simulating Verilog
  2. Cadence Encounter
  3. Hierarchical Design and Floorplanning

For other tutorials, please see the OSU wiki.