Difference between revisions of "VLSI Reading Group"

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(Suggested Papers)
(Suggested Papers)
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==Suggested Papers==
 
==Suggested Papers==
* [http://ieeexplore.ieee.org/xpls/abs_all.jsp?tp=&arnumber=753687 Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems], Vladimir Stojanovic and Vojin G. Oklobdzija. IEEE Journal of Solid-State Circuits, Vol. 34, No. 4, April 1999, pp. 536-548.
 
  
 
* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.
 
* [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],Ketan N. Patel, Igor L. Markov and John P. Hayes. IWLS 2003.

Revision as of 21:13, 4 January 2008

Overview

The reading group will meet in E2-209 one day a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation.

Participants

Schedule

Date Presenter Paper
row 1, cell 1 row 1, cell 2 row 1, cell 3

Suggested Papers

  • Geometric programming for circuit optimization, Boyd, S. P. and Kim, S. J. 2005. . In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.