Difference between revisions of "VLSI Reading Group"

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(Schedule)
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* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.
 
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.
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* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.
  
 
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].
 
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].

Revision as of 09:50, 31 January 2008

Overview

The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.

Participants

Schedule

Date Presenter Paper
1/10/08 - NOT MEETING
1/17/08 Matt M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity Matching, ASPDAC, Seoul, Korea, 2008, IN PRESS.
1/24/08 - NOT MEETING
1/31/08 Yaron Boyd, S. P. and Kim, S. J. Geometric programming for circuit optimization, In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.
1/31/08 Rigo F. Wang, X. Wu and Y. Xie, Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning, ASPDAC 2008.
2/7/08 Sheldon Ketan N. Patel, Igor L. Markov and John P. Hayes. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models, IWLS 2003.
2/7/08 Keven K.-C. Wu and D. Marculescu, Soft Error Rate Reduction Using Redundancy Addition and Removal , ASPDAC 2008.
2/14/08 Jeff Liang, X., Turgay, K., and Brooks, D. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD, 2007, pp 824-830.
2/14/08 Linh TBD
2/21/08 TBD TBD
2/21/08 TBD TBD
2/28/08 TBD TBD
2/28/08 TBD TBD
3/6/08 TBD TBD
3/6/08 TBD TBD
3/13/08 TBD TBD
3/13/08 TBD TBD

Potential Papers

  • Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. Large-scale circuit placement. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.