Difference between revisions of "VLSI Reading Group"

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| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008.  
 
| F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008.  
 
|-
 
|-
| 2/7/08
+
| 1/24/08
 +
| -
 +
| NOT MEETING
 +
|-
 +
| 2/14/08
 
| Sheldon
 
| Sheldon
 
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],  IWLS 2003.  
 
| Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models],  IWLS 2003.  
 
|-
 
|-
| 2/7/08
+
| 2/14/08
 
| Keven
 
| Keven
 
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.
 
| K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.
 
|-
 
|-
| 2/14/08
+
| 2/21/08
 
| Jeff
 
| Jeff
 
| Liang, X., Turgay, K., and Brooks, D.  [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830.   
 
| Liang, X., Turgay, K., and Brooks, D.  [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830.   
 
|-
 
|-
| 2/14/08
+
| 2/21/08
 
| Linh
 
| Linh
| TBD
 
|-
 
| 2/21/08
 
| TBD
 
| TBD
 
|-
 
| 2/21/08
 
| TBD
 
 
| TBD  
 
| TBD  
 
|-
 
|-
 
| 2/28/08
 
| 2/28/08
| TBD
+
| Mohammed
 
| TBD  
 
| TBD  
 
|-
 
|-
 
| 2/28/08
 
| 2/28/08
 
| TBD
 
| TBD
| TBD  
+
| TBD
 
|-
 
|-
 
| 3/6/08
 
| 3/6/08

Revision as of 14:15, 5 February 2008

Overview

The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.

Participants

Schedule

Date Presenter Paper
1/10/08 - NOT MEETING
1/17/08 Matt M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity Matching, ASPDAC, Seoul, Korea, 2008, IN PRESS.
1/24/08 - NOT MEETING
1/31/08 Yaron Boyd, S. P. and Kim, S. J. Geometric programming for circuit optimization, In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.
1/31/08 Rigo F. Wang, X. Wu and Y. Xie, Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning, ASPDAC 2008.
1/24/08 - NOT MEETING
2/14/08 Sheldon Ketan N. Patel, Igor L. Markov and John P. Hayes. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models, IWLS 2003.
2/14/08 Keven K.-C. Wu and D. Marculescu, Soft Error Rate Reduction Using Redundancy Addition and Removal , ASPDAC 2008.
2/21/08 Jeff Liang, X., Turgay, K., and Brooks, D. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD, 2007, pp 824-830.
2/21/08 Linh TBD
2/28/08 Mohammed TBD
2/28/08 TBD TBD
3/6/08 TBD TBD
3/6/08 TBD TBD
3/13/08 TBD TBD
3/13/08 TBD TBD

Potential Papers

  • Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. Large-scale circuit placement. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.