Difference between revisions of "VLSI Reading Group"

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==Overview==
 
==Overview==
The reading group will meet in E2-209 every Thursday for approximately 1 hour (12:15-1:15). Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.
+
The reading group will meet in E2-209 once a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.
  
==Participants==
+
==Spring 2008 Participants==
 
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]
 
* [http://www.soe.ucsc.edu/~mrg Matthew Guthaus]
* [http://www.soe.ucsc.edu/~rigo Rigo Dicochea]
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* Sheldon Logan
+
 
* Keven Woo
+
==Spring 2008 Schedule==
* Mohammed Jamil
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{| border="1"
* J. Semendari
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|-
* Yaron Kretchmer
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! Date
* Linh Hoang
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! Presenter
 +
! Paper
 +
|-
 +
| 4/3/08
 +
| Rigo
 +
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]"  Int'l Conf. On Computer Design (ICCD 2001), pp.328-333.
 +
|-
 +
| 4/3/08
 +
| Sheldon
 +
| TBD
 +
|}
 +
 
 +
==Potential Papers==
 +
 
 +
 
 +
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668.
 +
 
 +
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.
 +
 
 +
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.
 +
 
 +
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.
 +
 
 +
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf
 +
 
 +
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].
 +
 
  
 
==Winter 2008 Schedule==
 
==Winter 2008 Schedule==
Line 77: Line 103:
 
|-
 
|-
 
|}
 
|}
 
==Spring 2008 Schedule==
 
{| border="1"
 
|-
 
! Date
 
! Presenter
 
! Paper
 
|-
 
| 4/3/08
 
| Rigo
 
| S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]"  Int'l Conf. On Computer Design (ICCD 2001), pp.328-333.
 
|-
 
| 4/3/08
 
| Sheldon
 
| TBD
 
|}
 
 
==Potential Papers==
 
 
 
* A. B. Kahng, P. Sharma, and A. Zelikovsky, "[http://portal.acm.org/citation.cfm?id=1233639 Fill for Shallow Trench Isolation CMP]", Proc. ACM/IEEE Intl. Conf. on Computer-Aided Design, November 2006, pp. 661-668.
 
 
* S., Srivastava, A., Sharma, D., Sylvester, D., Blaauw, D., and Zolotov, V. 2005. [http://portal.acm.org/citation.cfm?id=1129702&jmp=cit&coll=portal&dl=ACM&CFID=7564954&CFTOKEN=49489343 Discrete Vt assignment and gate sizing using a self-snapping continuous formulation]. In Proceedings of the 2005 IEEE/ACM international Conference on Computer-Aided Design (San Jose, CA, November 06 - 10, 2005). International Conference on Computer Aided Design. IEEE Computer Society, Washington, DC, 705-712.
 
 
* Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. [http://portal.acm.org/citation.cfm?id=1059886 Large-scale circuit placement]. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.
 
 
* S.-C. Chang, M. Marek-Sadowska, and K.-T. Cheng, [http://ieeexplore.ieee.org/iel1/11994/00552082.pdf Perturb and Simplify: Multi-level Boolean Network Optimizer], IEEE Transactions on CAD, vol. 15, no. 12, pp. 1494-1504, December 1996.
 
 
* http://www.ece.rice.edu/~kmram/publications/dft03.pdf
 
 
* Other papers from [http://bacon.cse.ucsc.edu/papers ICCAD 2007].
 

Revision as of 10:41, 31 March 2008

Overview

The reading group will meet in E2-209 once a week for approximately 1 hour. Students will be selected to present an informal discussion of a chosen paper. Credit for the seminar is given based on your participation. You are welcome to bring your lunch.

Spring 2008 Participants


Spring 2008 Schedule

Date Presenter Paper
4/3/08 Rigo S. N. Adya and I. L. Markov, "Fixed-outline Floorplanning Through Better Local Search" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333.
4/3/08 Sheldon TBD

Potential Papers

  • Cong, J., Shinnerl, J. R., Xie, M., Kong, T., and Yuan, X. 2005. Large-scale circuit placement. ACM Trans. Des. Autom. Electron. Syst. 10, 2 (Apr. 2005), 389-430.


Winter 2008 Schedule

Date Presenter Paper
1/10/08 - NOT MEETING
1/17/08 Matt M.R. Guthaus, D. Sylvester, R.B. Brown. Clock Tree Synthesis with Data-path Sensitivity Matching, ASPDAC, Seoul, Korea, 2008, IN PRESS.
1/24/08 - NOT MEETING
1/31/08 Yaron Boyd, S. P. and Kim, S. J. Geometric programming for circuit optimization, In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.
1/31/08 Rigo F. Wang, X. Wu and Y. Xie, Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning, ASPDAC 2008.
2/07/08 - NOT MEETING
2/14/08 Sheldon Ketan N. Patel, Igor L. Markov and John P. Hayes. Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models, IWLS 2003.
2/14/08 Keven K.-C. Wu and D. Marculescu, Soft Error Rate Reduction Using Redundancy Addition and Removal , ASPDAC 2008.
2/21/08 Jeff Liang, X., Turgay, K., and Brooks, D. Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques. ICCAD, 2007, pp 824-830.
2/21/08 Jeff Cacti
2/28/08 Mohammed Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "HotSpot: a compact thermal modeling methodology for early-stage VLSI design," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.
2/28/08 Linh Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization. ICCAD 2007, pp 450-457.
3/6/08 NO MEETING
3/13/08 Janak H. Patel (UIUC) CMOS Process Variations: A "Critical Operation Point" hypothesis