- Each week, one person will present TWO papers. Everyone only presents one day.
- You must select papers that are less than one year old and in top conferences.
- You must think that the papers are VERY GOOD. To do this, you need to read the paper BEFORE you select it for the group. You may need to read several papers to find a good one.
- You must post your papers one week prior to your presentation.
|9/29/09||Sheldon Logan, Keven Woo||VLSI-SOC & ICCD practice|
|10/6/09||Seokjoong Kim||1. Lide Zhang, Robert P. Dick, Scheduled voltage scaling for increasing lifetime in the presence of NBTI, ASP-DAC 2009, 2. Yu Wang et al, Gate Replacement Techniques for Simultaneous Leakage and Aging Optimization, DATE2009|
|10/13/09||No 280G (VLSI-SOC conference)|
|10/20/09||Matthew Guthaus||How to review a research paper. Slides|
|10/27/09||Keven Woo||1. Yu Hu, Zhe Feng, Lei He, and Rupak Majumdar Robust FPGA Resynthesis Based on Fault-Tolerant Boolean Matching ICCAD 2008, 2. Shantanu Gupta, Amina Ansari, Shuguang Feng and Scott Maklhe Adaptive Online Testing for Efficient Hard Fault Detection ICCD 09|
|11/03/09||Sheldon Logan||1. Yufu Zhang and Ankur Srivastava Accurate Temperature Estimation Using Noisy Thermal Sensors DAC 2009 2. Xin Li, Yuchun Ma and Xianlong Hong A Novel Thermal Optimization Flow Using Incremental Floorplanning for 3D ICs ASPDAC 2009.|
|11/10/09||Jas Condley||1. Tharaka Dissanayake, Karu P. Esselle and Mehmet R. Yuce Dielectric Loaded Impedance Matching for Wideband Implanted Antennas IEEE Transactions on Microwave Theory and Techniques (Oct 2009).
2. Amirhossein Alimohammad and Bruce F. Cockburn FPGA-based Accelerator for the Verification of Leading-Edge Wireless Systems DAC 2009.
|11/17/09||Andrew W. Hill||1. Anderson, JH. Najm, Farid. Low-Power Programmable FPGA Routing Circuitry TVLSI 2009.
2. Ling, Liu. Olver, Neal. et. al. High-performance, energy-efficient platforms using in-socket FPGA accelerators FPGA '09.
|11/24/09||Marcelo Siero||1. Ankur Gupta, and Lyle N. Long, Character Recognition using Spiking Neural Networks IEEE Neural Networks Conference in Orlando Fla, Aug. 2007
2. Jayawan H. B. Wijekoo and Piotr Dudek Intetrated Circuit Implementation of a Cortical Neurona ] ISCAS 2008
3. Jayawan H. B. Wijekoo and Piotr Dudek Spike and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit. Proceeding of Intnl Joint Conference on NN, Orlando, Fla, USA, August 12-17, 2007
The 3rd paper is for reference only. You may also wish to look at the wiki on Hebbian Learning.
|12/1/09||Xuchu Hu||1.Rupesh S. Shelar An algorithm for routing with capacitance/distance constraints for clock distribution in microprocessors ISPD'09
2.Xiaoji Ye, Srinath Narasimhan, Peng Li, Leveraging efficient parallel pattern search for clock mesh optimization ICCAD'09. You can find the paper on ICCAD'09 disk on the shelf.