Crack I/F
- Constants: Cluster IDs
const ClusterIdType CLUSTER_AUNIT 2'b00 const ClusterIdType CLUSTER_BUNIT 2'b01 const ClusterIdType CLUSTER_CUNIT 2'b10 const ClusterIdType CLUSTER_MUNIT 2'b11
- LRegType
Range of Register 0..31 integer logical register 32..63 FP logical register 64..74 special use registers
Special Use Registers Definitions const LRegType LOG_ZERO 7'b0000000; const LRegType LOG_CEXC 7'd64; const LRegType LOG_ PSR 7'd65; const LRegType LOG_ WIM 7'd66; const LRegType LOG_ CWP 7'd67; const LRegType LOG_ TBR 7'd68; const LRegType LOG_ Y 7'd69; const LRegType LOG_ FSR 7'd70; const LRegType LOG_ ICC 7'd71; const LRegType LOG_ FCC 7'd672; const LRegType LOG_ PC 7'd73; const LRegType LOG_ TMP 7'd74;
- DInst_CRType
BoolType valid (1 bits)
The valid flag indicates that the associated instruction is a legal instruction packet. When this flag is set, the instruction is renamed by the ROB/RAT unit; a RAT and a ROB entry is allocated. This flag is passed through to the Scheduler (DInst_RRType valid flag).
BoolType slow (1 bits)
The slow flag indicates that the associated instruction has been tagged as a ‘long delay’ instruction like a LD/ST or FP. This flag is passed through to the Scheduler.
OPType op 10 bits)
The op field is SCORE’s encoded micro-code opcode. The 10 bit encoding is broken into three subsections: immediate instruction flag (1-bit), execution cluster (3-bits) and micro-instruction (6-bits).
IMMType imm (32 bits)
The imm field contains the immediate value contained in an immediate instruction. This field is limited by the 32-bit type definition. This field is valid if and only if the immediate instruction flag (use_imm) is set in the OPType.
BoolType expop (1 bits)
All ISA instructions are translated info SCORE micro-instructions and most have a one-to-one correspondence. For all of these instructions, the expop flag is asserted. However, some ISA instructions must be decomposed into multiple SCORE micro-instructions; in this case, the first instruction in the micro-instruction sequence sets this flag indicating the beginning of the micro-instruction sequence. Other instructions in the sequence de-assert this flag. Micro-instruction sequences cannot be longer than three instructions (i.e. 1-0 and 1-0-0). The instruction address is the same for all micro-instructions in such a sequence.
BoolType cexc (1 bits)
Asserting the cexc flag indicates that the associated instruction is a FP type and requires that the Special Register CEXC be updated with the same renamed destination register used when renaming this instruction. A CEXE flag is maintained in the ROB entry to instruct the Retire RAT to update its CEXC Special Register when this instruction is retired.
BoolType aexc_clear (1 bits)
The aexc_clear flag indicates that when this instruction is retired, AEXC (accumulated FP status bits) must be cleared. This flag is retained in the ROB and used when constructing the EXCRetireType (sent to the C_unit) when the instruction is RETIRED.
BoolType icc (1 bits)
Asserting the icc flag indicates that the associated instruction is a FX type and requires that the Special Register ICC be updated with the same renamed destination register used when renaming this instruction. A icc flag is maintained in the ROB entry to instruct the Retire RAT to update its icc Special Register when this instruction is retired.
BoolType useY (1 bits)
Asserting the useY flag indicates that the associated instruction is a FP type and requires that the Special Register USEY be updated with the same renamed destination register used when renaming this instruction. A useY flag is maintained in the ROB entry to instruct the Retire RAT to update its useY Special Register when this instruction is retired.
BPredStateType state (9 bits)
• BoolType taken (1 bit) • OBPPtrType obp_ptr (8 bits)
Cluster IdType id (3 bits)
The id field maps the instruction to one of the four (4) internal FU clusters in the CE. This field is appended to the physical register location to for the PRegType.
LRegType ldest (7 bits)
The value of this register is the architectural destination register associated with this instruction.
LRegType lsrc1 (7 bits)
The value of this register is the architectural register associated with SRC1 of this instruction.
LRegType lsrc2 (7 bits)
The value of this register is the architectural register associated with SRC2 of this instruction.
