Difference between revisions of "Ce"

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(Overall Interface for INPUT to Compute Engine & OUTPUT from Compute Engine)
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Revision as of 00:12, 31 March 2009

== Compute Engine Design Specifications ==

The COMPUTE ENGINE of SCOORE is responsible for all the calculations of the processor. SCOORE is a clustered architecture, we have FOUR main units which comprise the COMPUTE ENGINE.

  1. AUNIT is responsible for all the "simple arithmetic operations" of the CPU.(Single Port)
  2. BUNIT is responsible for branch operations. (Dual Port)
  3. CUNIT handles all floating point operations. (Single Port)
  4. MUNIT handles all Load and Store operations. (Dual Port)

A more detailed description of each individual block is given below.


Overall Interface for INPUT to Compute Engine & OUTPUT from Compute Engine

CLOCK and RESET are Global Inputs to the Compute Engine.

Inputs to Compute Engine FROM Select:

  1. aunit_dinst
  2. bunit_dinst_1
  3. bunit_dinst_2
  4. cunit_dinst
  5. munit_dinst_1
  6. munit_dinst_2

Outputs from Compute Engine TO Select and RAT/ROB:

  1. Aunit_DoneType
  2. Bunit_Br_DoneType
  3. Bunit_ALU_DoneType
  4. Cunit_DoneType
SELECT - CACHE - RATROB
SELECT
COMPUTE ENGINE
AUNIT BUNIT CUNIT MUNIT
RAT/ROB - SELECT - CACHE
RAT/ROB - SELECT

Individual Unit Descriptions

Each of the four clusters in the CE holds 128 registers in its Register File. There are a total of 512 registers. A 9-bit binary number is assigned to each register. Since there are only 512 registers, the highest 2-bits are indicative of the CE cluster/unit to which they belong.

Register Numbers and Corresponding Units
Register Number Highest 2 bits Compute Engine (CE)
0 - 127 00 A Unit RF
128 - 255 01 B Unit RF
256 - 383 10 C Unit RF
384 - 511 11 M Unit RF

AUNIT

aunit_stage1
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
aunit_stage2
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
salu
 -Single Cycle Execution Stage
write_back
 Reg. File

The AUNIT executes the following SPARC V8 instructions:

BUNIT

bunit_stage1
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
bunit_stage2
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
balu/salu
 -Single Cycle Execution Stage
write_back
 Reg. File

The BUNIT executes the following SPARC V8 instructions:

CUNIT

cunit_stage1
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
cunit_stage2
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
FPU
 -Multiple Cycle Execution Stage
write_back
 Reg. File

The CUNIT executes the following SPARC V8 instructions:

MUNIT

munit_stage1
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
munit_stage2
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
CACHE
 -Multiple Cycle Execution Stage
write_back
 Reg. File

The MUNIT executes the following SPARC V8 instructions:


--Rigo Dicochea 09:47, 30 March 2009 (PDT)