Difference between revisions of "Ce"

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== == Compute Engine Design Specifications == ==
 
== == Compute Engine Design Specifications == ==
  
 +
ASIC AREA Estimate(dc_shell):
 +
 +
FPGA LUT Estimate(synplify_pro): 35,500 LUTs
  
 
The COMPUTE ENGINE of SCOORE is responsible for all the calculations of the processor. SCOORE is a clustered architecture, we have FOUR main units which comprise the COMPUTE ENGINE.   
 
The COMPUTE ENGINE of SCOORE is responsible for all the calculations of the processor. SCOORE is a clustered architecture, we have FOUR main units which comprise the COMPUTE ENGINE.   
  
−
# AUNIT is responsible for all the "simple arithmetic operations" of the CPU.(Single Port)   
+
# AUNIT is responsible for all the "simple arithmetic operations" ie. add,sub,shift,AND, XOR... of the CPU.(Single Port)   
−
# BUNIT is responsible for branch operations. (Dual Port)
+
# BUNIT is responsible for branch operations ie. BNE, BGE.... (Dual Port)
 
# CUNIT handles all floating point operations. (Single Port)
 
# CUNIT handles all floating point operations. (Single Port)
 
# MUNIT handles all Load and Store operations. (Dual Port)  
 
# MUNIT handles all Load and Store operations. (Dual Port)  
Line 15: Line 18:
  
 
== Overall Interface for INPUT to Compute Engine & OUTPUT from Compute Engine ==
 
== Overall Interface for INPUT to Compute Engine & OUTPUT from Compute Engine ==
 +
CLOCK and RESET are Global Inputs to the Compute Engine.
 +
 +
Inputs to Compute Engine(CE) FROM Select:
 +
At most CE can receive 6 instructions/cycle from Select.  Listed below is a sample of what could be sent in "best" case.
 +
 +
#aunit_dinst - This instruction would qualify as a simple arithmetic instruction.
 +
#bunit_dinst_1 - This instruction would be a branch operation.
 +
#bunit_dinst_2 - This would be an alu operation.
 +
#cunit_dinst - This would be a floating point operation.
 +
#munit_dinst_1 - This would be a load operation.
 +
#munit_dinst_2 - This would be a store operation.
 +
 +
Input to Compute Engine FROM RAT/ROB:
 +
 +
#clear - asserted when branch mis-prediction occurs.
 +
 +
Input to Compute Engine FROM CACHE:
 +
 +
#load_data - data to be loaded into register from memory.
 +
 +
Outputs from Compute Engine TO Select:
 +
#Aunit_DoneType
 +
#Bunit_Br_DoneType
 +
#Bunit_ALU_DoneType
 +
#Cunit_DoneType
 +
 +
Ouput from Compute Engine to RAT/ROB:
 +
 +
#DoneType Struct containing RID for retirement of instruction
 +
 +
Output from Compute Engine to Cache:
 +
#Request To Load from memory or to Store into memory
  
 
{|
 
{|
 
|style="text-align:center" |
 
|style="text-align:center" |
 
{| style="border:2px dashed blue" width="300pt" cellspacing="0"
 
{| style="border:2px dashed blue" width="300pt" cellspacing="0"
−
   |+ SELECT
+
   |+ CACHE - SELECT - RATROB
 
   |- style="height:150px; vertical-align:top"
 
   |- style="height:150px; vertical-align:top"
−
   !SELECT
+
   !CACHE - SELECT - RATROB
 
|}
 
|}
 
| style="text-align:center"|
 
| style="text-align:center"|
−
{| border="1" width="300pt" cellspacing="0"
+
{| border="1" width="300pt" height="900px" cellspacing="0"
 
   |+ COMPUTE ENGINE
 
   |+ COMPUTE ENGINE
−
   |- style="height:150px; vertical-align:top"
+
   |- style="height=500px; vertical-align:top"
−
   !AUNIT
+
   |- align="center"
−
   !BUNIT
+
  || AUNIT  
−
   !CUNIT
+
   |- align="center"
−
   !MUNIT
+
  || BUNIT  
 +
   |- align="center"
 +
  || CUNIT  
 +
   |- align="center"
 +
  || MUNIT  
 +
  |- align="center"
 
|}
 
|}
 +
 
| style="text-align:center"|
 
| style="text-align:center"|
 
{| style="border:2px dashed blue" width="300pt" cellspacing="0"
 
{| style="border:2px dashed blue" width="300pt" cellspacing="0"
−
   |+ RAT/ROB - SELECT
+
   |+ CACHE - SELECT - RATROB
 
   |- style="height:150px; vertical-align:top"
 
   |- style="height:150px; vertical-align:top"
−
   !RAT/ROB - SELECT
+
   !CACHE - SELECT - RATROB
 
|}
 
|}
 
|}
 
|}
−
 
  
 
== Individual Unit Descriptions ==
 
== Individual Unit Descriptions ==
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   -Update Logic
 
   -Update Logic
 
   !salu
 
   !salu
−
   -Execution Stage
+
   -Single Cycle Execution Stage
 
   !write_back
 
   !write_back
 
   Reg. File
 
   Reg. File
 
|}
 
|}
 +
[[Image:Aunit.jpeg|1100x425px]]
 +
The AUNIT executes the following SPARC V8 instructions:
 +
 
== BUNIT ==
 
== BUNIT ==
 
{| border="1" width="300pt" cellspacing="0"
 
{| border="1" width="300pt" cellspacing="0"
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   -Update Logic
 
   -Update Logic
 
   !balu/salu
 
   !balu/salu
−
   -Execution Stage
+
   -Single Cycle Execution Stage
 
   !write_back
 
   !write_back
 
   Reg. File
 
   Reg. File
 
|}
 
|}
 +
[[Image:Bunit.jpeg|1100x425px]]
 +
The BUNIT executes the following SPARC V8 instructions:
 +
 
== CUNIT ==
 
== CUNIT ==
 
{| border="1" width="300pt" cellspacing="0"
 
{| border="1" width="300pt" cellspacing="0"
Line 105: Line 151:
 
   -Update Logic
 
   -Update Logic
 
   !FPU
 
   !FPU
−
   -Execution Stage
+
   -Multiple Cycle Execution Stage
 
   !write_back
 
   !write_back
 
   Reg. File
 
   Reg. File
 
|}
 
|}
 +
The CUNIT executes the following SPARC V8 instructions:
 +
 
== MUNIT ==
 
== MUNIT ==
 
{| border="1" width="300pt" cellspacing="0"
 
{| border="1" width="300pt" cellspacing="0"
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   -Update Logic
 
   -Update Logic
 
   !CACHE
 
   !CACHE
−
   -Execution Stage
+
   -Multiple Cycle Execution Stage
 
   !write_back
 
   !write_back
 
   Reg. File
 
   Reg. File
 
|}
 
|}
 +
The MUNIT executes the following SPARC V8 instructions:
 +
 +
 +
 
--[[User:Rigo Dicochea|Rigo Dicochea]] 09:47, 30 March 2009 (PDT)
 
--[[User:Rigo Dicochea|Rigo Dicochea]] 09:47, 30 March 2009 (PDT)

Latest revision as of 16:14, 15 May 2009

== Compute Engine Design Specifications ==

ASIC AREA Estimate(dc_shell):

FPGA LUT Estimate(synplify_pro): 35,500 LUTs

The COMPUTE ENGINE of SCOORE is responsible for all the calculations of the processor. SCOORE is a clustered architecture, we have FOUR main units which comprise the COMPUTE ENGINE.

  1. AUNIT is responsible for all the "simple arithmetic operations" ie. add,sub,shift,AND, XOR... of the CPU.(Single Port)
  2. BUNIT is responsible for branch operations ie. BNE, BGE.... (Dual Port)
  3. CUNIT handles all floating point operations. (Single Port)
  4. MUNIT handles all Load and Store operations. (Dual Port)

A more detailed description of each individual block is given below.


Overall Interface for INPUT to Compute Engine & OUTPUT from Compute Engine

CLOCK and RESET are Global Inputs to the Compute Engine.

Inputs to Compute Engine(CE) FROM Select: At most CE can receive 6 instructions/cycle from Select. Listed below is a sample of what could be sent in "best" case.

  1. aunit_dinst - This instruction would qualify as a simple arithmetic instruction.
  2. bunit_dinst_1 - This instruction would be a branch operation.
  3. bunit_dinst_2 - This would be an alu operation.
  4. cunit_dinst - This would be a floating point operation.
  5. munit_dinst_1 - This would be a load operation.
  6. munit_dinst_2 - This would be a store operation.

Input to Compute Engine FROM RAT/ROB:

  1. clear - asserted when branch mis-prediction occurs.

Input to Compute Engine FROM CACHE:

  1. load_data - data to be loaded into register from memory.

Outputs from Compute Engine TO Select:

  1. Aunit_DoneType
  2. Bunit_Br_DoneType
  3. Bunit_ALU_DoneType
  4. Cunit_DoneType

Ouput from Compute Engine to RAT/ROB:

  1. DoneType Struct containing RID for retirement of instruction

Output from Compute Engine to Cache:

  1. Request To Load from memory or to Store into memory
CACHE - SELECT - RATROB
CACHE - SELECT - RATROB
COMPUTE ENGINE
AUNIT
BUNIT
CUNIT
MUNIT
CACHE - SELECT - RATROB
CACHE - SELECT - RATROB

Individual Unit Descriptions

Each of the four clusters in the CE holds 128 registers in its Register File. There are a total of 512 registers. A 9-bit binary number is assigned to each register. Since there are only 512 registers, the highest 2-bits are indicative of the CE cluster/unit to which they belong.

Register Numbers and Corresponding Units
Register Number Highest 2 bits Compute Engine (CE)
0 - 127 00 A Unit RF
128 - 255 01 B Unit RF
256 - 383 10 C Unit RF
384 - 511 11 M Unit RF

AUNIT

aunit_stage1 
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
aunit_stage2 
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
salu 
 -Single Cycle Execution Stage
write_back 
 Reg. File

Aunit.jpeg The AUNIT executes the following SPARC V8 instructions:

BUNIT

bunit_stage1 
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
bunit_stage2 
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
balu/salu 
 -Single Cycle Execution Stage
write_back 
 Reg. File

Bunit.jpeg The BUNIT executes the following SPARC V8 instructions:

CUNIT

cunit_stage1 
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
cunit_stage2 
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
FPU 
 -Multiple Cycle Execution Stage
write_back 
 Reg. File

The CUNIT executes the following SPARC V8 instructions:

MUNIT

munit_stage1 
 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic
munit_stage2 
 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic
CACHE 
 -Multiple Cycle Execution Stage
write_back 
 Reg. File

The MUNIT executes the following SPARC V8 instructions:


--Rigo Dicochea 09:47, 30 March 2009 (PDT)

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