Difference between revisions of "Ce"

Latest revision as of 16:14, 15 May 2009

== Compute Engine Design Specifications ==

ASIC AREA Estimate(dc_shell):

FPGA LUT Estimate(synplify_pro): 35,500 LUTs

The COMPUTE ENGINE of SCOORE is responsible for all the calculations of the processor. SCOORE is a clustered architecture, we have FOUR main units which comprise the COMPUTE ENGINE.

1. AUNIT is responsible for all the "simple arithmetic operations" ie. add,sub,shift,AND, XOR... of the CPU.(Single Port)
2. BUNIT is responsible for branch operations ie. BNE, BGE.... (Dual Port)
3. CUNIT handles all floating point operations. (Single Port)
4. MUNIT handles all Load and Store operations. (Dual Port)

A more detailed description of each individual block is given below.

Overall Interface for INPUT to Compute Engine & OUTPUT from Compute Engine

CLOCK and RESET are Global Inputs to the Compute Engine.

Inputs to Compute Engine(CE) FROM Select: At most CE can receive 6 instructions/cycle from Select. Listed below is a sample of what could be sent in "best" case.

1. aunit_dinst - This instruction would qualify as a simple arithmetic instruction.
2. bunit_dinst_1 - This instruction would be a branch operation.
3. bunit_dinst_2 - This would be an alu operation.
4. cunit_dinst - This would be a floating point operation.
5. munit_dinst_1 - This would be a load operation.
6. munit_dinst_2 - This would be a store operation.

Input to Compute Engine FROM RAT/ROB:

1. clear - asserted when branch mis-prediction occurs.

Input to Compute Engine FROM CACHE:

1. load_data - data to be loaded into register from memory.

Outputs from Compute Engine TO Select:

1. Aunit_DoneType
2. Bunit_Br_DoneType
3. Bunit_ALU_DoneType
4. Cunit_DoneType

Ouput from Compute Engine to RAT/ROB:

1. DoneType Struct containing RID for retirement of instruction

Output from Compute Engine to Cache:

1. Request To Load from memory or to Store into memory

Individual Unit Descriptions

Each of the four clusters in the CE holds 128 registers in its Register File. There are a total of 512 registers. A 9-bit binary number is assigned to each register. Since there are only 512 registers, the highest 2-bits are indicative of the CE cluster/unit to which they belong.

AUNIT

 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic

 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic

 -Single Cycle Execution Stage

 Reg. File

The AUNIT executes the following SPARC V8 instructions:

BUNIT

 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic

 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic

 -Single Cycle Execution Stage

 Reg. File

The BUNIT executes the following SPARC V8 instructions:

CUNIT

 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic

 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic

 -Multiple Cycle Execution Stage

 Reg. File

The CUNIT executes the following SPARC V8 instructions:

MUNIT

 -Local/Ext/Imm Src Sel. Logic
 -Reset/Busy Logic

 -Reservation Station Logic
 -Forwarding Logic
 -Update Logic

 -Multiple Cycle Execution Stage

 Reg. File

The MUNIT executes the following SPARC V8 instructions:

--Rigo Dicochea 09:47, 30 March 2009 (PDT)