Difference between revisions of "280G F10"
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| 11/02/10 | | 11/02/10 | ||
|Jas Condley | |Jas Condley | ||
| − | | | + | | [http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=4810337 Design Methodology of High Performance On-Chip Global Interconnect Using Terminated Transmission-Line] |
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| 11/08/10 9:30am | | 11/08/10 9:30am | ||
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| 11/16/10 | | 11/16/10 | ||
| Ian | | Ian | ||
| − | | | + | | [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5401228 A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms] |
|- | |- | ||
| 11/23/10 | | 11/23/10 | ||
|Sheldon | |Sheldon | ||
| − | | | + | | [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5419910 On-chip power network optimization with decoupling capacitors and controlled-ESRs] |
|- | |- | ||
| 11/30/10 | | 11/30/10 | ||
| − | | | + | |Chasen |
| − | | | + | | [http://portal.acm.org/citation.cfm?id=1815968 Understanding sources of inefficiency in general-purpose chips] |
|} | |} | ||
Latest revision as of 09:52, 27 November 2010
- You may only take this class Pass/Fail. (If you do not, you will receive a non-passing grade.)
- Each week, one person will present ONE paper. Everyone only presents one day.
- You must select papers that are less than one year old and in top conferences.
- You must think that the papers are VERY GOOD. To do this, you need to read the paper BEFORE you select it for the group. You may need to read several papers to find a good one.
- You must post your papers one week prior to your presentation.
| Date | Presenter | Paper |
|---|---|---|
| 10/05/10 | Xuchu | An efficient phase detector connection structure for the skew synchronization system (DAC2010) |
| 10/12/10 | Seokjoong | On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (DATE2010) |
| 10/19/10 | No Meeting | |
| 10/26/10 | Andrew W. Hill | Xetal-Pro: An Ultra-Low Energy and High Throughput SIMD Processor (DAC2010) |
| 11/02/10 | Jas Condley | Design Methodology of High Performance On-Chip Global Interconnect Using Terminated Transmission-Line |
| 11/08/10 9:30am | Dr. Paul Morton | Thinking Outside the Rectilinear Box: A Mathematical and Algorithmic Foundation for Physical Design using Nonrectilinear Shapes |
| 11/09/10 | On MONDAY | |
| 11/16/10 | Ian | A Methodology for Power Aware High-Level Synthesis of Co-processors from Software Algorithms |
| 11/23/10 | Sheldon | On-chip power network optimization with decoupling capacitors and controlled-ESRs |
| 11/30/10 | Chasen | Understanding sources of inefficiency in general-purpose chips |
