Difference between revisions of "Standard-Cell Tutorials"
From Vlsiwiki
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# [[OSU Technology Setup]]<BR> | # [[OSU Technology Setup]]<BR> | ||
| + | # [[Other Technology Setups]]<BR> | ||
# [[Synopsys Design Compiler]]<BR> | # [[Synopsys Design Compiler]]<BR> | ||
# [[Advanced Synopsys Design Compiler]]<BR> | # [[Advanced Synopsys Design Compiler]]<BR> | ||
Revision as of 18:40, 4 May 2008
- OSU Technology Setup
- Other Technology Setups
- Synopsys Design Compiler
- Advanced Synopsys Design Compiler
- Simulating Verilog
- Cadence Encounter
- Hierarchical Design and Floorplanning
- Library Modification/Creation
For other tutorials, please see the OSU wiki.
