Difference between revisions of "Ce"
From Vlsiwiki
| Line 10: | Line 10: | ||
A more detailed description of each individual block is given below. | A more detailed description of each individual block is given below. | ||
| + | {| | ||
{| | {| | ||
{| border="1" width="300pt" cellspacing="0" | {| border="1" width="300pt" cellspacing="0" | ||
| Line 23: | Line 24: | ||
!CE0 | !CE0 | ||
|} | |} | ||
| − | + | |} | |
{| border="1" width="300pt" cellspacing="0" | {| border="1" width="300pt" cellspacing="0" | ||
Revision as of 17:15, 30 March 2009
== Compute Engine Design Specifications ==
The COMPUTE ENGINE of SCOORE is responsible for all the calculations of the processor. SCOORE is a clustered architecture, we have FOUR main units which comprise the COMPUTE ENGINE.
- AUNIT is responsible for all the "simple arithmetic operations" of the CPU.(Single Port)
- BUNIT is responsible for branch operations. (Dual Port)
- CUNIT handles all floating point operations. (Single Port)
- MUNIT handles all Load and Store operations. (Dual Port)
A more detailed description of each individual block is given below.
| SE0 | SE1 |
|---|
| CE0 |
|---|
| aunit_stage1 | aunit_stage2 | salu | write_back |
|---|
| bunit_stage1 | bunit_stage2 | balu/salu | write_back |
|---|
| cunit_stage1 | cunit_stage2 | FPU | write_back |
|---|
| munit_stage1 | munit_stage2 | CACHE | write_back |
|---|
--Rigo Dicochea 09:47, 30 March 2009 (PDT)
