Difference between revisions of "Standard-Cell Tutorials"
From Vlsiwiki
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# [[Simulating Verilog]]<BR> | # [[Simulating Verilog]]<BR> | ||
# [[Cadence Encounter]]<BR> | # [[Cadence Encounter]]<BR> | ||
| + | # [[Hierarchical Design and Floorplanning]] | ||
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki]. | For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki]. | ||
Revision as of 21:19, 5 February 2008
- OSU Technology Setup
- Synopsys Design Compiler
- Advanced Synopsys Design Compiler
- Simulating Verilog
- Cadence Encounter
- Hierarchical Design and Floorplanning
For other tutorials, please see the OSU wiki.
