Difference between revisions of "Standard-Cell Tutorials"
From Vlsiwiki
| Line 1: | Line 1: | ||
# [[OSU Technology Setup]]<BR> | # [[OSU Technology Setup]]<BR> | ||
# [[Other Technology Setups]]<BR> | # [[Other Technology Setups]]<BR> | ||
| − | # [[Synopsys Design Compiler]]<BR> | + | # [[Synopsys Design Compiler]] ([[General Synopsys Synthesis Script]])<BR> |
# [[Advanced Synopsys Design Compiler]]<BR> | # [[Advanced Synopsys Design Compiler]]<BR> | ||
# [[Simulating Verilog]]<BR> | # [[Simulating Verilog]]<BR> | ||
Revision as of 18:46, 4 May 2008
- OSU Technology Setup
- Other Technology Setups
- Synopsys Design Compiler (General Synopsys Synthesis Script)
- Advanced Synopsys Design Compiler
- Simulating Verilog
- Cadence Encounter
- Hierarchical Design and Floorplanning
- Library Modification/Creation
For other tutorials, please see the OSU wiki.
