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| | == Old Schedules == | | == Old Schedules == |
| − | ===Spring 2008===
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| − | {| border="1"
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| − | |-
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| − | ! Date
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| − | ! Presenter
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| − | ! Paper
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| − | |-
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| − | | 4/7/08
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| − | | Rigo
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| − | | S. N. Adya and I. L. Markov, "[http://vlsicad.eecs.umich.edu/BK/parquet/iccd_2001_floorplan.pdf Fixed-outline Floorplanning Through Better Local Search]" Int'l Conf. On Computer Design (ICCD 2001), pp.328-333.
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| − | |-
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| − | | 4/7/08
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| − | | Sheldon
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| − | | Rao, R. M., Liu, F., Burns, J. L., and Brown, R. B. [http://ieeexplore.ieee.org/Xplore/login.jsp?url=/iel5/8895/28127/01257884.pdf?isnumber=28127&prod=CNF&arnumber=1257884&arSt=+689&ared=+692&arAuthor=Rao%2C+R.M.%3B+Liu%2C+F.%3B+Burns%2C+J.L.%3B+Brown%2C+R.B. A Heuristic to Determine Low Leakage Sleep State Vectors for CMOS Combinational Circuits]. ICCAD, 2003, pp 689-697
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| − | |-
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| − | | 4/14/08
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| − | |
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| − | | No class (@ ISPD)
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| − | |-
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| − | | 4/21/08
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| − | | Matt
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| − | | Satisfiability (No Paper)
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| − | |-
| |
| − | | 4/28/08
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| − | | Derek
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| − | | Verilog-A & Current Work
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| − | |-
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| − | | 5/5/08
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| − | | -
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| − | | Out of Town
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| − | |-
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| − | | 5/12/08
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| − | | Jeff
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| − | | B. Mohammad, M. Saint-Laurent, P. Bassett, and J. Abraham. [http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=4479707 Cache Design for Low Power and High Yield]. ISQED, 2008, pp 103-107.
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| − | |-
| |
| − | | 5/19/08
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| − | | Keven
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| − | | J. Sheaeffer D. Luebke K. Skadron [http://www.cs.virginia.edu/~skadron/Papers/sheaffer_gh2007.pdf A Hardware Redundancy and Recovery Mechanism for Reliable Scientific Computation on Graphics Processors]. ACM, 2007
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| − | |-
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| − | | 5/26/08
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| − | | Nobody
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| − | | No class (Memorial Day)
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| − | |-
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| − | | 6/2/08
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| − | | -
| |
| − | | No Class
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| − | |
| |
| − | |-
| |
| − | | 6/9/08
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| − | | -
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| − | | No Class (@ DAC)
| |
| − | |}
| |
| − | === Winter 2008 ===
| |
| − | {| border="1"
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| − | |-
| |
| − | ! Date
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| − | ! Presenter
| |
| − | ! Paper
| |
| − | |-
| |
| − | | 1/10/08
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| − | | -
| |
| − | | NOT MEETING
| |
| − | |-
| |
| − | | 1/17/08
| |
| − | | Matt
| |
| − | | M.R. Guthaus, D. Sylvester, R.B. Brown. [http://bacon.cse.ucsc.edu/papers/guthaus-aspdac08.pdf Clock Tree Synthesis with Data-path Sensitivity Matching], ASPDAC, Seoul, Korea, 2008, IN PRESS.
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| − | |-
| |
| − | | 1/24/08
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| − | | -
| |
| − | | NOT MEETING
| |
| − | |-
| |
| − | | 1/31/08
| |
| − | | Yaron
| |
| − | | Boyd, S. P. and Kim, S. J. [http://portal.acm.org/citation.cfm?id=1055148 Geometric programming for circuit optimization], In Proceedings of the 2005 international Symposium on Physical Design (San Francisco, California, USA, April 03 - 06, 2005). ISPD '05. ACM, New York, NY, 44-46.
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| − |
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| − | |-
| |
| − | | 1/31/08
| |
| − | | Rigo
| |
| − | | F. Wang, X. Wu and Y. Xie, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p2_1A-1.pdf Variability-Driven Module Selection with Joint Design Time Optimization and Post-Silicon Tuning], ASPDAC 2008.
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| − | |-
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| − | | 2/07/08
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| − | | -
| |
| − | | NOT MEETING
| |
| − | |-
| |
| − | | 2/14/08
| |
| − | | Sheldon
| |
| − | | Ketan N. Patel, Igor L. Markov and John P. Hayes. [http://citeseer.ist.psu.edu/644440.html Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models], IWLS 2003.
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| − | |-
| |
| − | | 2/14/08
| |
| − | | Keven
| |
| − | | K.-C. Wu and D. Marculescu, [http://bacon.cse.ucsc.edu/papers/aspdac_2008/p559_7A-1.pdf Soft Error Rate Reduction Using Redundancy Addition and Removal ], ASPDAC 2008.
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| − | |-
| |
| − | | 2/21/08
| |
| − | | Jeff
| |
| − | | Liang, X., Turgay, K., and Brooks, D. [http://portal.acm.org/citation.cfm?id=1326073.1326245&coll=&dl=GUIDE&type=series&idx=SERIES388&part=series&WantType=Proceedings&title=ICCAD# Architectural power models for SRAM and CAM structures based on hybrid analytical/empirical techniques]. ICCAD, 2007, pp 824-830.
| |
| − | |-
| |
| − | | 2/21/08
| |
| − | | Jeff
| |
| − | | [http://www.ece.ubc.ca/~stevew/papers/html/jssc96/paper.html Cacti]
| |
| − | |-
| |
| − | | 2/28/08
| |
| − | | Mohammed
| |
| − | | Wei Huang; Ghosh, S.; Velusamy, S.; Sankaranarayanan, K.; Skadron, K.; Stan, M.R., "[http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=1650228 HotSpot: a compact thermal modeling methodology for early-stage VLSI design]," Very Large Scale Integration (VLSI) Systems, IEEE Transactions on , vol.14, no.5, pp. 501-513, May 2006.
| |
| − | |-
| |
| − | | 2/28/08
| |
| − | | Linh
| |
| − | | Xin Li, Taylor, Brian YuTsun Chien, Pileggi, Lawrence T. [http://www.ieeexplore.ieee.org/xpls/abs_all.jsp?isnumber=4397223&arnumber=4397306&count=153&index=82 Adaptive post-silicon tuning for analog circuits: concept, analysis and optimization.] ICCAD 2007, pp 450-457.
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| − | |-
| |
| − | | 3/6/08
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| − | |
| |
| − | | NO MEETING
| |
| − | |-
| |
| − | | 3/13/08
| |
| − | | Janak H. Patel (UIUC)
| |
| − | | CMOS Process Variations: A "Critical Operation Point" hypothesis
| |
| − | |-
| |
| − | |}
| |
The reading group will meet in E2-209 on Tuesdays 2-3pm. Students will be selected to present an informal discussion of a chosen paper. Credit (pass/fail only) for the seminar is given based on your participation.
