Difference between revisions of "Standard-Cell Tutorials"
From Vlsiwiki
| Line 5: | Line 5: | ||
# [[Simulating Verilog]]<BR> | # [[Simulating Verilog]]<BR> | ||
# [[Cadence Encounter]]<BR> | # [[Cadence Encounter]]<BR> | ||
| + | # [[Primetime]]<BR> | ||
# [[Hierarchical Design and Floorplanning]] | # [[Hierarchical Design and Floorplanning]] | ||
# [[Library Modification/Creation]] | # [[Library Modification/Creation]] | ||
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki]. | For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki]. | ||
Revision as of 00:40, 17 February 2011
- OSU Technology Setup
- Other Technology Setups
- Synopsys Design Compiler (General Synopsys Synthesis Script)
- Advanced Synopsys Design Compiler
- Simulating Verilog
- Cadence Encounter
- Primetime
- Hierarchical Design and Floorplanning
- Library Modification/Creation
For other tutorials, please see the OSU wiki.
