Difference between revisions of "Standard-Cell Tutorials"
From Vlsiwiki
Line 1: | Line 1: | ||
# [[OSU Technology Setup]]<BR> | # [[OSU Technology Setup]]<BR> | ||
# [[Other Technology Setups]]<BR> | # [[Other Technology Setups]]<BR> | ||
− | |||
# [[Advanced Synopsys Design Compiler]]<BR> | # [[Advanced Synopsys Design Compiler]]<BR> | ||
# [[Simulating Verilog]]<BR> | # [[Simulating Verilog]]<BR> | ||
# [[Cadence Encounter]]<BR> | # [[Cadence Encounter]]<BR> | ||
− | |||
# [[Hierarchical Design and Floorplanning]] | # [[Hierarchical Design and Floorplanning]] | ||
# [[Library Modification/Creation]] | # [[Library Modification/Creation]] | ||
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki]. | For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki]. |
Revision as of 00:20, 28 May 2015
- OSU Technology Setup
- Other Technology Setups
- Advanced Synopsys Design Compiler
- Simulating Verilog
- Cadence Encounter
- Hierarchical Design and Floorplanning
- Library Modification/Creation
For other tutorials, please see the OSU wiki.