Standard-Cell Tutorials
From Vlsiwiki
- OSU Technology Setup
- Other Technology Setups
- Synopsys Design Compiler (General Synopsys Synthesis Script)
- Advanced Synopsys Design Compiler
- Simulating Verilog
- Cadence Encounter
- Primetime
- Hierarchical Design and Floorplanning
- Library Modification/Creation
For other tutorials, please see the OSU wiki.