Standard-Cell Tutorials
From Vlsiwiki
Revision as of 21:19, 5 February 2008 by 128.114.59.176 (Talk)
- OSU Technology Setup
- Synopsys Design Compiler
- Advanced Synopsys Design Compiler
- Simulating Verilog
- Cadence Encounter
- Hierarchical Design and Floorplanning
For other tutorials, please see the OSU wiki.
