Standard-Cell Tutorials

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Revision as of 21:48, 8 February 2008 by 67.117.130.206 (Talk)

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  1. OSU Technology Setup
  2. Synopsys Design Compiler
  3. Advanced Synopsys Design Compiler
  4. Simulating Verilog
  5. Cadence Encounter
  6. Hierarchical Design and Floorplanning
  7. Library Modification/Creation

For other tutorials, please see the OSU wiki.

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