Simulating Verilog

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This section will briefly talk about how to simulate Verilog. You can simulate Verilog that is either behavioral, gate-level, or back-annotated (with delays). Behavioral and gate-level are done in the same way, but back annotate requires an extra system call in your Verilog.

The first thing I recommend that you do is to create a "project.f" file that is just a list of all of your Verilog files. Like this:


Running Verilog

You can use three different Verilog simulators: ncverilog ("ncverilog"), VCS ("vcs") or verilog-XL ("verilog"). There is also a 4th GNU simulator called Icarus Verilog that you can install on your own computer.


Simply run:

ncverilog -f project.f

Look for any warnings or errors. At the end of the output, you should see:

Simulation complete via $finish(1) at time 10 US + 0
./sram_tb.v:64 	$finish();
ncsim> exit

If you want to view the outputs in a GUI, you can run:

ncverilog -f project.f +gui

This will compile the verilog and run SimVision. There is more on SimVision in the Advanced Testbenches tutorial.

You can also put these extra arguments in the project.f file.


To run VCS:

vcs +v2k -f project.f

Specifying -R on the command line will run it immediately and not produce the simv binary.


Verilog-XL does not support much of Verilog 2001. However, given that, it can be run in the same way:

verilog -f project.f


verilog -f project.f +gui

Icarus Verilog

Icarus can be run like this:

iverilog -c project.f

Note that this will *compile* the verilog into a binary called "a.out". To actually run the Verilog, you must now run it:


Icarus Verilog seems to be more lenient on errors in Verilog code. You should make sure it compiles in NCVerilog too. Icarus does not come with a GUI, so you will either need to use the $display command or install GTKWave.

Simulating Verilog in Ultrasim

For non-digital simulations, you can simulate a structural Verilog netlist in Ultrasim as well. However, you need to supply the spice subcircuits of the library:



In order to back-annotate, you should output an SDF file from either Synopsys Design Compiler (before physical design) or from SoC encounter. Each SDF format is sometimes different, so you may have to hack it to get it to work. Common incompatibilities are the dilimiting characters in hierarchical names, for example. Carefully watch the warnings!

The system call to back-annotate is like this:

initial begin
  $sdf_annotate("gate/lfsr-final.sdf", l0);

where lfsr.sdf is the SDF file and l0 is the instance name of the top module that you synthesized. Note that you should not be using your unsynthesized verilog now. Use the output from synthesis in the file, gate/lfsr-final.v, along with your original testbench.