Difference between revisions of "Standard-Cell Tutorials"

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# [[Simulating Verilog]]<BR>
 
# [[Simulating Verilog]]<BR>
 
# [[Cadence Encounter]]<BR>
 
# [[Cadence Encounter]]<BR>
 +
# [[Hierarchical Design and Floorplanning]]
  
 
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].
 
For other tutorials, please see the [http://avatar.ecen.okstate.edu/wiki/index.php/Tutorials#Cadence OSU wiki].

Revision as of 14:19, 5 February 2008

  1. OSU Technology Setup
  2. Synopsys Design Compiler
  3. Advanced Synopsys Design Compiler
  4. Simulating Verilog
  5. Cadence Encounter
  6. Hierarchical Design and Floorplanning

For other tutorials, please see the OSU wiki.