Difference between revisions of "SCOORE"
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Jose Renau (Talk | contribs) (New page: === SCOORE Pipeline === Image:scoorepipe.jpg) |
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| + | Major SCOORE blocks: | ||
| + | |||
| + | * [[bpred]]: Branch predictor with BTB, OGEHL, RAS, BIT, and instruction predecode | ||
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| + | * [[L0I]]: Instruction cache | ||
| + | |||
| + | * [[crack]]: Instruction decode/crack creates uOPs from SPARC V8. | ||
| + | |||
| + | * [[ratrob]]: Rename and Reorder buffer | ||
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| + | * [[scheduler]]: Long latency instruction scheduler window. | ||
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| + | * [[select]]: Instruction select stage to enforce structural hazards | ||
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| + | * [[ce]]: Compute Engine | ||
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| + | * [[L0D]]: Speculative L0 data cache | ||
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| + | * [[L1]]: L1 cache | ||
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| + | === Checkout SCOORE === | ||
Revision as of 18:48, 23 June 2008
SCOORE Pipeline
Major SCOORE blocks:
- bpred: Branch predictor with BTB, OGEHL, RAS, BIT, and instruction predecode
- L0I: Instruction cache
- crack: Instruction decode/crack creates uOPs from SPARC V8.
- ratrob: Rename and Reorder buffer
- scheduler: Long latency instruction scheduler window.
- select: Instruction select stage to enforce structural hazards
- ce: Compute Engine
- L0D: Speculative L0 data cache
- L1: L1 cache
