Difference between revisions of "MASC"
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Step 1: Create a directory, preferably named the same thing as your design top level. | Step 1: Create a directory, preferably named the same thing as your design top level. | ||
| − | For example if my design is named alu, | + | For example: if my design is named alu, |
I would create a directory by the name of alu. | I would create a directory by the name of alu. | ||
Step 2: Create an rtl directory inside the design directory. | Step 2: Create an rtl directory inside the design directory. | ||
| − | For example alu/rtl | + | For example: alu/rtl |
Step 3: All design rtl should reside in the rtl directory. | Step 3: All design rtl should reside in the rtl directory. | ||
| − | For example alu/rtl/alu.v alu/rtl/alu_mem.v alu/rtl/alu_fifo.v | + | For example: alu/rtl/alu.v alu/rtl/alu_mem.v alu/rtl/alu_fifo.v |
Step 4: In the alu directory create an xml file. The xml file must have the same name as the directory. | Step 4: In the alu directory create an xml file. The xml file must have the same name as the directory. | ||
| − | For example alu/alu.xml | + | For example: alu/alu.xml |
Step 5: The xml file must contain the following tags. | Step 5: The xml file must contain the following tags. | ||
| + | For example: | ||
<project name="alu"> | <project name="alu"> | ||
<requires>common</requires> | <requires>common</requires> | ||
Revision as of 19:00, 9 April 2012
Micro Architecture Santa Cruz wiki projects.
Contents
Conferences
Repositories
- ESESC Superscalar Simulator
- SCOORE Santa Cruz Out-of-Order Risc Engine
- MTHD Multitouch Hardware Description
- Gource Software Version Control Visualization
Students
- Desktop Setup Instructions to setup your desktop
- VIM Tips, tricks, and shortcuts
Synthesis Setup
MASC uses a unified compilation environment which requires the use of the command rake to synthesize designs. To synthesize your design follow the steps below:
Step 1: Create a directory, preferably named the same thing as your design top level.
For example: if my design is named alu,
I would create a directory by the name of alu.
Step 2: Create an rtl directory inside the design directory.
For example: alu/rtl
Step 3: All design rtl should reside in the rtl directory.
For example: alu/rtl/alu.v alu/rtl/alu_mem.v alu/rtl/alu_fifo.v
Step 4: In the alu directory create an xml file. The xml file must have the same name as the directory.
For example: alu/alu.xml
Step 5: The xml file must contain the following tags.
For example:
<project name="alu">
<requires>common</requires>
<requires>rnet</requires>
<requires>storage</requires>
<requires>retry</requires>
<asic frequency="1400" tech="90" suite="dc"/>
<asic base="alu"/>
<catalyst base="alu" test=""/>
<verify base="alu"/>
<fpga base="alu" tool="synplify"/>
<testbench base="alu_tb" suite="vcs">
<CC></CC>
<verilog>tests/</verilog>
<tab>tests/</tab>
<source>
</source>
</testbench>
<regression target="test">alu_tb</regression>
<regression target="asic">alu</regression>
<regression target="fpga">alu</regression>
</project>
Testbenching
LEON / Nallatech
- LEON 3 Complete Place and Route of LEON 3 Core on XC 5VFX130T
- NALLATECH Develop complete interface flow
