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| | * [[Synthesis Setup|Synthesis Setup]] | | * [[Synthesis Setup|Synthesis Setup]] |
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| − | MASC uses a unified compilation environment which requires the use of the command rake to synthesize designs.
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| − | To synthesize your design follow the steps below:
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| − | Step 1: Create a directory, preferably named the same thing as your design top level.
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| − | For example: if my design is named alu,
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| − | I would create a directory by the name of alu.
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| − | Step 2: Create an rtl directory inside the design directory.
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| − | For example: alu/rtl
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| − | Step 3: All design rtl should reside in the rtl directory.
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| − | For example: alu/rtl/alu.v alu/rtl/alu_mem.v alu/rtl/alu_fifo.v
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| − | Step 4: In the alu directory create an xml file. The xml file must have the same name as the directory.
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| − | For example: alu/alu.xml
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| − | Step 5: The xml file must contain the following tags.
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| − | For example:
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| − | <project name="alu">
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| − | <requires>common</requires>
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| − | <requires>rnet</requires>
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| − | <requires>storage</requires>
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| − | <requires>retry</requires>
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| − | <asic frequency="1400" tech="90" suite="dc"/>
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| − | <asic base="alu"/>
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| − | <catalyst base="alu" test=""/>
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| − | <verify base="alu"/>
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| − | <fpga base="alu" tool="synplify"/>
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| − | <testbench base="alu_tb" suite="vcs">
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| − | <CC></CC>
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| − | <verilog>tests/</verilog>
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| − | <tab>tests/</tab>
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| − | <source>
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| − | </source>
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| − | </testbench>
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| − | <regression target="test">alu_tb</regression>
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| − | <regression target="asic">alu</regression>
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| − | <regression target="fpga">alu</regression>
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| − | </project>
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| − | Step 6: From the design directory type rake.
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| − | For example: (from alu/ )type "rake"
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| − | All options for the current design should be displayed on the screen.
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| − | rigo @ mada0 ~/mascrtl/projects/tapeout/alu $ rake
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| − | (in /mada/users/rigo/mascrtl)
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| − | rake all # Run everything!
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| − | rake asic:all # Run all ASIC tasks.
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| − | rake asic:alu_top # Run "alu_top" with ASIC.
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| − | rake catalyst:all # Create the Catalyst directory
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| − | rake catalyst:alu_top # Create "alu_top" for Catalyst.
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| − | rake clean # Remove any temporary products.
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| − | rake clobber # Remove any generated file.
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| − | rake default # Show a list of available tasks.
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| − | rake fpga:all # Run all FPGA tasks.
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| − | rake fpga:alu_top # Run "alu_top" with "synplify" FPGA.
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| − | rake regression:all # Run all regression tasks.
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| − | rake regression:clean # clean all regression tasks.
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| − | rake regression:clobber # clobber all regression tasks.
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| − | rake rverilog:all # Create the Verilog/Ruby generated files.
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| − | rake test:all # Run all test benches.
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| − | rake verify:all # Run all verify tasks.
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| − | rake verify:alu_top # Run "alu_top" with Formality.
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| − | General Options:
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| − | full=1 ; Let any module to be a target
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| − | v=1 ; Do not launch program execution
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| − | FPGA Options:
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| − | tool=num ; synplify
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| − | ASIC Options:
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| − | tech=num ; Technology (90, 65...)
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| − | frequency=num ; Frequency in MHz (900, 140)
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| − | suite=string ; ASIC suite (dc, pt, rc, soc)
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| − | TEST Options:
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| − | suite=string ; Test suite (vsim, vcs, ncsim, gcc)
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| − | gui=1 ; Invoke gui for testbench (vsim, vcs)
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| − | console=1 ; Console Mode. (verify, dc_shell) Only with v=1.
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| − | do="run -all" ; ModelSim -do line, ex do="do wave.do; run -all" (GUI Only)
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| − | grid=1 ; Submit testbench(s) to Sun Grid (vsim, vcs)
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| − | SDF=1 ; Do timing run (must compile with ASIC first)
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| − | SAIF=1 ; Dump a SAIF and VCD for power analysis (it could be used with SDF=1)
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| − | ttb=0 ; Disable automatic generation of testbench files
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| − | args= ; Pass args to tb. Use Quotes to pass multiple args
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| − | Touch the ttb rtl file to regenerate the ttb
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| − | Step 7: Type "rake asic:alu full=1 v=1
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| − | Output: (in /mada/users/rigo/mascrtl)
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| − | ./dc_alu.sh
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| − | ./dct_alu.sh
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| − | ./dc_alu.sh
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| − | ./dct_alu.sh
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| − | Step 8: type ./dc_alu.sh
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| | ==Testbenching== | | ==Testbenching== |
