Difference between revisions of "SCOORE"

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Major SCOORE blocks:
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* [[bpred]]: Branch predictor with BTB, OGEHL, RAS, BIT, and instruction predecode
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* [[L0I]]: Instruction cache
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* [[crack]]: Instruction decode/crack creates uOPs from SPARC V8.
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* [[ratrob]]: Rename and Reorder buffer
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* [[scheduler]]: Long latency instruction scheduler window.
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* [[select]]: Instruction select stage to enforce structural hazards
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* [[ce]]: Compute Engine
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* [[L0D]]: Speculative L0 data cache
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* [[L1]]: L1 cache
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=== [[SCOORE Synthesis]] ===
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SCOORE targets ASIC and FPGA. To simplify configurations the synos script automatically generates configuration files for all the tools.
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=== [[SCOORE Coding Style]] ===
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SCOORE uses a subset of System Verilog. The subset is selected to maximize reuse while still working in all the synthesis tools.
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=== [[FPGA Boot]] ===
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SCOORE has a dual ASIC/FPGA target. We target many FPGAs as long as they
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are big enough. This document explains how to bring up a SCOORE board.
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=== [[Term Definitions]] ===
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This section explains the main names that we use in SCOORE. This is a convention/agreement
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so that everybody uses the same language.
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In addition, [http://ramp.eecs.berkeley.edu/ RAMP] shares many goals with the SCOORE project.
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This link explains some of the SCOORE constructs from a RAMP perspective.

Latest revision as of 14:41, 27 March 2009

SCOORE Pipeline

Scoorepipe.jpg

Major SCOORE blocks:

  • bpred: Branch predictor with BTB, OGEHL, RAS, BIT, and instruction predecode
  • L0I: Instruction cache
  • crack: Instruction decode/crack creates uOPs from SPARC V8.
  • ratrob: Rename and Reorder buffer
  • scheduler: Long latency instruction scheduler window.
  • select: Instruction select stage to enforce structural hazards
  • ce: Compute Engine
  • L0D: Speculative L0 data cache
  • L1: L1 cache

SCOORE Synthesis

SCOORE targets ASIC and FPGA. To simplify configurations the synos script automatically generates configuration files for all the tools.

SCOORE Coding Style

SCOORE uses a subset of System Verilog. The subset is selected to maximize reuse while still working in all the synthesis tools.

FPGA Boot

SCOORE has a dual ASIC/FPGA target. We target many FPGAs as long as they are big enough. This document explains how to bring up a SCOORE board.

Term Definitions

This section explains the main names that we use in SCOORE. This is a convention/agreement so that everybody uses the same language.

In addition, RAMP shares many goals with the SCOORE project. This link explains some of the SCOORE constructs from a RAMP perspective.