Difference between revisions of "SCOORE"

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=== [[SCOORE Coding Style]] ===
 
=== [[SCOORE Coding Style]] ===
 
SCOORE uses a subset of System Verilog. The subset is selected to maximize reuse while still working in all the synthesis tools.
 
SCOORE uses a subset of System Verilog. The subset is selected to maximize reuse while still working in all the synthesis tools.
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=== [[FPGA Boot]] ===

Revision as of 00:28, 3 December 2008

SCOORE Pipeline

Scoorepipe.jpg

Major SCOORE blocks:

  • bpred: Branch predictor with BTB, OGEHL, RAS, BIT, and instruction predecode
  • L0I: Instruction cache
  • crack: Instruction decode/crack creates uOPs from SPARC V8.
  • ratrob: Rename and Reorder buffer
  • scheduler: Long latency instruction scheduler window.
  • select: Instruction select stage to enforce structural hazards
  • ce: Compute Engine
  • L0D: Speculative L0 data cache
  • L1: L1 cache

SCOORE Synthesis

SCOORE targets ASIC and FPGA. To simplify configurations the synos script automatically generates configuration files for all the tools.

SCOORE Coding Style

SCOORE uses a subset of System Verilog. The subset is selected to maximize reuse while still working in all the synthesis tools.

FPGA Boot